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Polycide Bipolar Transistor Process

IP.com Disclosure Number: IPCOM000048163D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR [+4]

Abstract

A narrow transistor basewidth (about 1,000 Angstroms) can be achieved by forming the base by diffusion out of a polysilicon layer. The following process uses a shallow polysilicon layer as the diffusion source for both the intrinsic and extrinsic bases, and a metal silicide layer is then added to lower the extrinsic base resistance. The specific process is as follows: (1) Form the transistor subcollector 10, epitaxial layer 11, isolation (for example, recessed oxide isolation) 12 and reach-through 13 upon substrate 8, as shown in Fig. 1. (2) Chemically vapor deposit a 500 Acronym polysilicon layer 14 on the wafer.

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Polycide Bipolar Transistor Process

A narrow transistor basewidth (about 1,000 Angstroms) can be achieved by forming the base by diffusion out of a polysilicon layer. The following process uses a shallow polysilicon layer as the diffusion source for both the intrinsic and extrinsic bases, and a metal silicide layer is then added to lower the extrinsic base resistance. The specific process is as follows: (1) Form the transistor subcollector 10, epitaxial layer

11, isolation (for example, recessed oxide isolation)

12 and reach-through 13 upon substrate 8, as shown in

Fig. 1.

(2) Chemically vapor deposit a 500 Acronym polysilicon

layer 14 on the wafer. Dope the polysilicon with a 5

KeV boron implant, then cap the polysilicon with 1,000

Acronym of chemically vapor deposited silicon dioxide

layer 15, and drive in the boron to form the intrinsic

and extrinsic bases 16, as shown in Fig. 2. The desired

base profile at this point is shown in Fig. 3.

(3) Remove the silicon dioxide layer 15. Co-sputter or

co-evaporate a 1,000 Acronym layer of tungsten silicide

layer 17 onto the polysilicon. Stabilize the silicide

layer with an 800 degree C, 30-minute anneal, and then

chemically vapor deposit a 4,000 Acronym silicon dioxide

layer 18 onto the silicide to produce the Fig. 4

structure.

(4) Mask off the designated extrinsic base regions with

photo-resist (not shown), then reactive ion etch off

the silicon dioxide layer 18 preferentially in a CF(4)/

H(2) plasma, the silicide layer 17 in a CF(4) + 20%

O(2), and the polysilicon layer 14 in Cl(2)/Ar. The

silicide will have approximately a 5 to 1 etch rate ra...