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Layout for Lateral NPN Protective Device Enhancing Chip Wireability

IP.com Disclosure Number: IPCOM000048164D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR [+3]

Abstract

Devices used to protect MOSFETs (metal oxide silicon field effect transistors) against electrostatic discharges (ESD) must be evaluated by the following criteria: (1) The maximum discharge energy that they can shunt without undergoing damage. (2) Their voltage clamping. (3) Their leakage current conduction and input capacitance.

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Layout for Lateral NPN Protective Device Enhancing Chip Wireability

Devices used to protect MOSFETs (metal oxide silicon field effect transistors) against electrostatic discharges (ESD) must be evaluated by the following criteria: (1) The maximum discharge energy that they can shunt without

undergoing damage.

(2) Their voltage clamping.

(3) Their leakage current conduction and input capacitance.

A lateral NPN (LNPN) transistor embedded in thick silicon dioxide has been shown to meet items (1) and (2). Moreover, if the threshold voltage of the thick silicon dioxide at zero source to substrate bias, V(SS), is a few volts positive, its subthreshold leakage current will be small enough to satisfy the first requirement in (3).

The LNPN transistor as a protective device is in a common emitter configuration, and to insure its voltage snapback after the breakdown of its collector junction, its three terminals must be properly connected to the high and low potential of the ESD which appear at the input/output (I/O) pads and substrate ring, respectively. These interconnections are shown in Fig. 1, and the following considerations apply to them: (1) Series resistance of the interconnection 9 from I/O pad

to the collector C and from the substrate ring 10 to

the emitter E should be small to obtain good voltage

clamping and forward bias the emitter well. Fig. 2

shows a conventional layout which simply uses metal

straps to the collector 1, and to the emitter 2.

(2) The base region B is connected to the reference potential

of the substrate ring by means of the spreading resistance

R(x) of the substrate.

(3) Since the emitter E is at substrate potential, the

surrounding substrate surface is at the lowest threshold

voltage possible. To minimize the associated

subthreshold conduction, the best solution is to place the

metal gate electrode 3 of Fig. 2 around the emitter

periphery and connect it to substrate potential. Metal

gate 3 extends downward to merge with the metal connection

2 and upward to overlap the collector which, being

closest, is the most likely drain for subthreshold

leakage to the emitter.

Although metal straps 1 and 2 and gate 3 are the best solutions to the problems that they are addressed to, they also use chip area and block wiring channels carrying signals and power to and from the I/O pads. Thus, a conflict has arisen between the above LNPN layout and the wiring requirements of random access memory chips where silicon area is at a premium. To resolve this conflict, a new LNPN layout has been made.

Fig. 3 shows one version of the lateral NPN layout which does

1

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not employ metal for...