Browse Prior Art Database

High Performance MESFET Structure

IP.com Disclosure Number: IPCOM000048166D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+2]

Abstract

The requirements of a successful very large scale integration (VLSI) technology impose severe restrictions on power consumption and demands on the speed of the basic device. Metal silicon field effect transistors (MESFETs) look very attractive as device sizes shrink for VLSI for memory and logic applications. The method described is a silicon MESFET, but GaAs, CdS, GeC and other materials can also be used in the formation of this MESFET.

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High Performance MESFET Structure

The requirements of a successful very large scale integration (VLSI) technology impose severe restrictions on power consumption and demands on the speed of the basic device. Metal silicon field effect transistors (MESFETs) look very attractive as device sizes shrink for VLSI for memory and logic applications. The method described is a silicon MESFET, but GaAs, CdS, GeC and other materials can also be used in the formation of this MESFET.

The following process fabricates a very small MESFET with high speed and small resistance in the triode region: 1. An N epitaxial layer 10 of about 0.5 micrometer is

grown upon a P substrate 11.

2. Isolation regions 12 are formed by any of the conventional

techniques to isolate silicon areas designated

to contain MESFET devices, as shown in Fig. 1.

3. A SiO(2) layer 13 of about 500 Angstrom is grown over the

surface of the epitaxial layer 10, followed by a 1000 to

2000 Acronym layer 14 of Si(3)N(4) upon layer 13, as

seen in Fig. 2.

4. The silicon dioxide and silicon nitride layers 13 and 14,

respectively, are etched using conventional lithographic

techniques to leave only the designated gate regions

covered, as shown in Fig. 3.

5. Chemical vapor deposited layer 15 of silicon dioxide of

about 3000 Angstrom is deposited, followed by a blanket

reactive ion etching of the silicon dioxide layer to

substantially remove the horizontal layer and

substantially leave the vertical layer, as shown

in Fig. 4....