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Automatic Electrical Defect Detection on MLC Redistribution Sublaminates

IP.com Disclosure Number: IPCOM000048174D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Simpson, RA: AUTHOR [+2]

Abstract

Sublamination can significantly reduce the manufacturing capacity needed to produce a given number of multilayer ceramic (MLC) packaging substrates. It consists of dividing the stack of green sheets needed to produce a complete laminated substrate into sets of consecutive layers, grouped by function, that are pressed to form sublaminates and tested independently. A set of tested sublaminates is pressed to form a complete laminate.

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Automatic Electrical Defect Detection on MLC Redistribution Sublaminates

Sublamination can significantly reduce the manufacturing capacity needed to produce a given number of multilayer ceramic (MLC) packaging substrates. It consists of dividing the stack of green sheets needed to produce a complete laminated substrate into sets of consecutive layers, grouped by function, that are pressed to form sublaminates and tested independently. A set of tested sublaminates is pressed to form a complete laminate.

One sublaminate consists of the top surface metallurgy and redistribution layers. The wiring on the "redistribution" sublaminate remains within the area of the individual chip sites. It consists of a central array of chip-to-substrate interconnections (chip vias) which are redistributed to a double row of pads used for testing or engineering changes. These pads are wired to interconnections on the bottom of the sublaminate. Since the wiring is contained within the area of each chip site, testing can be accomplished a site at a time.

A simple means of automating detection of redistribution sublaminate electrical defects is described below. It makes use of signals, generated by contactless electron beam test methods, that indicate the presence of electrical connection between chip and bottom surface interconnections. It provides the following features: 1. A simple defect detection means, based on the counting

of known numbers of chip vias and/or pads that should

be detected during electrical testing.

2. High throughput capability by providing automatic

defect detection.

3. Defect classification (opens/shorts and repairable/

non-repairable).

4. Defect localization by chip number.

5. Inexpensive implementation, since no computer control

or data processing is required.

6. Extendability to defect localization within each chip

site, and test run results logging.

Fig. 1 shows the chip via and EC pad arrays at a single chip site on the top surface of a redistribution sublaminate. The scans of the electron beam during the "reading" operation are shown by the arrowed lines. The pattern generator, shown in Fig. 2, provides a fixed increment step raster scan, rather than the sweep raster scans used by systems relying on operator detection of defects. For "opens" inspection, the EC pad scan is initiated only if a preceding chip via scan has detected "opens". If a corresponding number of EC pad signals is missing, the "open" must be in the connection to the bottom surface and is therefore repairable by bypassing it using EC pad to EC pad wiring. If no EC pad signals are missing, the "open" exists between via and pad in one of the redistribution layers and is therefore unrepairable. In the case of shorts, no repair is possible, so further identification (other than just detection) is superfluous.

Fig. 2 shows the defect detection, identification and recording circuitry. The amplified photomulti...