Browse Prior Art Database

Self Aligned Silicide Buried Contacts

IP.com Disclosure Number: IPCOM000048177D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 4 page(s) / 69K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR

Abstract

Two implementations of conventional buried contact between a polysilicon layer 2 and a diffusion region 3 are shown in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 43% of the total text.

Page 1 of 4

Self Aligned Silicide Buried Contacts

Two implementations of conventional buried contact between a polysilicon layer 2 and a diffusion region 3 are shown in Fig. 1.

In region (A), a typical contact between a polysilicon interconnection and a diffused region is illustrated, while in region
(B) the polysilicon gate 4 is used to form the contact. Both are advantageous in that the contacting polysilicon layer 2 is also the source of N-type doping species, typically phosphorus, which diffuse through hole 6 in the thin silicon dioxide layer 7. The resulting N-type phosphorus region 3 is then self aligned with respect to the contacting polysilicon layer and the adjacent arsenic doped region 8. Nevertheless, despite this self alignment, buried contacts are not free from alignment tolerances. The contact mask used to define holes 6 must be aligned with respect to the subsequent gate mask. Thus, in region (A), the near edge 9 of the polysilicon gate must be spaced from the hole 6 and likewise for the far edge 10 in region
(B).

Other undesirable features of conventional buried contacts arise from the use of phosphorus to dope the polysilicon layer. Phosphorus diffused regions 3 are two or three times deeper than arsenic regions 8, and hence their sidewall junction capacitance is accordingly larger. Moreover, in region (B) the larger lateral diffusion of phosphorus increases the Delta L bias (Delta L equals L/mask/ - L/wafer/), where L/mask/ and L/wafer/ are the channel lengths at mask and wafer levels, respectively. Therefore, it is necessary to increase the gate length at mask level to obtain the channel length of conventional devices at wafer level. For instance, the mask gate length for region (B) is increased to 7.5 micrometers in order to obtain the wafer channel length of a conventional device with a mask gate length of 4.5 micrometers.

A buried contact, fabricated by means of abutting the silicide growth on adjacent polysilicon and diffusion regions, results in a contact that is completely self-aligned even though the doping impurities in the polysilicon layer are prevented from diffusing into the underlying substrate. Consequently, the junction capacitance of the contacted diffusion and gate length of the adjacent device are not increased by the presence of this buried contact. The concept is incorporated into a silicide process sequence to improve density at the cost of one extra masking operation. The process is as follows:

(1) Conventional operations are used to form the recessed silicon dioxide isolation region 11 and thin silicon dioxide layer 13 which is then covered with an N+ polysilicon layer followed by a silicon dioxide silicon nitride cap, C (Fig. 2).

(2) The oxide nitride cap, C, is patterned and the polysilicon layer is isotropically etched to form the polysilicon gate 15 and interconnection 16 both with well tapered sidewalls, as shown in Fig. 2. The disclosed buried contacts are to be formed between these sidewalls an...