Browse Prior Art Database

Memory Error Correction Without ECC

IP.com Disclosure Number: IPCOM000048184D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Neves, F: AUTHOR [+2]

Abstract

Single bit error correction is achieved through the use of a parity bit to detect the presence of a single bit error and the application of a complement read write algorithm to correct the error. Single hard errors are corrected by the provision of only one extra bit rather than the plurality of extra bits required by ECC (error correction code) and thus makes the present technique particularly attractive to small memory system users.

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Memory Error Correction Without ECC

Single bit error correction is achieved through the use of a parity bit to detect the presence of a single bit error and the application of a complement read write algorithm to correct the error. Single hard errors are corrected by the provision of only one extra bit rather than the plurality of extra bits required by ECC (error correction code) and thus makes the present technique particularly attractive to small memory system users.

The extra bit is a parity bit which is the exclusive OR of all the bits of the data word. Any erroneous data bit causes the data word to have parity opposite to that originally generated. A bad parity indication flags the CPU (central processing unit), for example, through an interrupt condition, to call attention to the presence of a single bad bit in the data word.

The CPU responds by enabling custom external logic or an internal routine to perform a complement read write algorithm on the memory location in error. The complement read write algorithm, in effect, is equivalent to the read complement write algorithm disclosed in the IBM Technical Disclosure Bulletin 13, 2190 (January 1971). An example of the complement read write algorithm is shown below.

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