Browse Prior Art Database

Interrupt Mode in Signal Processor

IP.com Disclosure Number: IPCOM000048201D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR [+2]

Abstract

This is a method for handling interrupt requests in a signal process based on the architecture of Fig. 1.

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Interrupt Mode in Signal Processor

This is a method for handling interrupt requests in a signal process based on the architecture of Fig. 1.

The signal processor includes a conventional structure, i.e., a first portion comprising two input registers X and Y feeding an arithmetic and logic unit (ALU) through two gates G1 and G2 and an accumulator (ACCU) being fed by the ALU output. In addition. due to the product of applications, such as digital filtering, for instance, a second portion has been attached to the first portion. The second portion is a multiplier constantly performing the multiplication of X register contents by Y register contents and feeding the result into the ALU through gate G1. For cycle timing purposes, the multiplier has been made to include a first multiplier section feeding a pipeline register (PR) and a second multiplier section connected to the output of the PR and, in turn, feeding an output register (RM).

With this structure, during an operating cycle the first multiplier performs the first half of the multiplication of X register contents (e.g.,A) (e.g., A) by Y register contents (e.g.,
B). During the next cycle, the output of the first multiplier is fed into PR while a new couple of data (e.g., C/D) is loaded into X and Y registers, and the second multiplier performs the remaining part of the multiplication of A by B. More precisely, a timing sequence, for example, may be represented by the following table.

Cycle N-3 N-2 N-1 N N+1 Reg X/Y A/B C/D E/F Pipeline
Reg A.B C.D E.F RM A.B C.D Instruction Load Load Load RM not RM not A/B C/D E/F to be to be

approaches approaches approaches used used

X/Y X/Y X/Y

Address in RPC N-2...