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Browse Prior Art Database

Central Control Unit Branch Trace Mechanism

IP.com Disclosure Number: IPCOM000048203D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Bonifas, D: AUTHOR [+4]

Abstract

This mechanism is to be used in a central control unit (CCU) working under control of an n-level program (PGM) stored in a main memory. Each time a branch operation is executed, it stores in a CCU main memory table, the successive branch addresses, on condition that these addresses are within low and high address limits and that the branch instruction was actually executed under specified interrupt levels. When the trace table is full, the CCU can be stopped or any other appropriate action may be undertaken. A BRANCH OPERATION is defined as follows: a. A true branch instruction has been executed, and the conditions for branching were net. b. The instruction address register (IAR) was modified by a CCU instruction execution. c.

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Central Control Unit Branch Trace Mechanism

This mechanism is to be used in a central control unit (CCU) working under control of an n-level program (PGM) stored in a main memory. Each time a branch operation is executed, it stores in a CCU main memory table, the successive branch addresses, on condition that these addresses are within low and high address limits and that the branch instruction was actually executed under specified interrupt levels. When the trace table is full, the CCU can be stopped or any other appropriate action may be undertaken. A BRANCH OPERATION is defined as follows:

a. A true branch instruction has been executed, and the

conditions for branching were net.

b. The instruction address register (IAR) was modified

by a CCU instruction execution.

c. Current PGM level operation has been interrupted or

exited and a new interrupt level has been entered even if

it is under the same interrupt level, whether this

happens on a Program Controlled Interrupt (PCI). an exit

or an external interrupt.

The phrase "under specified interrupt levels" means that a set of interrupt levels has to be specified in a Branch Trace level control register, and the branch trace shall be performed if the branch operations are executed under one of those specified levels, or if one of those specified interrupt levels is entered or exited via an interrupt or exit.

If it is desired, the trace table can be wrapped around when full and re-used right away, without missing any branches taken. The branch trace can be disabled at any time by resetting a branch trace mode bit, thus freezing the trace table.

Each entry in this table is 8 bytes long (byte 0 to byte 7 from left to right). The beginning address of this table must be loaded in a Branch Trace Table Address Register and the length of this table in bytes must be loaded in a Branch Table Table Count Register.

Each time a BRANCH OPERATION is performed, the table records the "come from" and "go to" addressed, and the "come from" and and "go to" program levels, in the following manner: TRACE TABLE ENTRY

0 1 2 3 4 5 6 7

"come

Type of from" "come from" address level "go to" "Branch" Level Address True branch instruction current Address of same as Branch Address program Instruction

IAR modifying level byte 0 New Modified instruction IAR previous Address of last new Address of

1

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Program program instruction program first instr. interrupt level executed under level executed previous level under new

prog. level

EXIT program Address of EXIT program Address of instruction level instruction level first inst. exited resumed executed

after after level

EXIT exit, under

go to level

If specified, when the table is full and the count register reaches zero, a Branch Trace Table Pointer is automatically reset to point back to the beginning of the table, and the count register is reloaded with table size, and the trace goes on, not losing any branch taken. This enables the keeping of the trace of th...