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Timing Variations in a Mono Clocking Scheme

IP.com Disclosure Number: IPCOM000048208D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Froment, JC: AUTHOR [+4]

Abstract

In a central control unit (CCU), this proposal allows the length of specific CCU cycles to be increased with a minimum performance impact since it retains the advantages of a mono clocking scheme.

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Timing Variations in a Mono Clocking Scheme

In a central control unit (CCU), this proposal allows the length of specific CCU cycles to be increased with a minimum performance impact since it retains the advantages of a mono clocking scheme.

The CCU of a communications controller or a central processing system is controlled cycle by cycle by control words stored in a read only storage (ROS). The execution of any instruction needs a variable number of cycles. For such a CCU it may happen that the last operation which takes place in the last cycle needs a longer duration than a clock cycle. Providing two cycles would impact performance heavily. Another solution is to provide a slightly longer cycle. For a load instruction reading the CCU main store, the data from main store has to be written in the local store and working registers; this storage operation takes place during the two last CCU cycles. A path delay analysis shows that it exceeds two CCU cycles by a fraction of one cycle. Therefore, the last cycle of the load instructions has an increased length. As the same ROS control word is used for the two cycles of the storage operation, a STORAGE BUSY signal is used to differentiate those two cycles.

As shown on the drawing, a ROS bit, called "EXTENDED CYCLE BIT" is added in the ROS control word. It is set to one by the CCU microcode when the CCU cycle has to be extended. This bit is latched, as are all other ROS control word bits, and ANDed with the STORAGE BUSY...