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Address Hashing Circuit for Memory with Nonchangeable Address Block

IP.com Disclosure Number: IPCOM000048217D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Braidt, JW: AUTHOR [+2]

Abstract

In a system in which a memory has two independently addressable cards and has circuits for simultaneously performing a refresh operation on one card while a normal memory access is made to the other card, a simple address hashing circuit causes memory addresses to occur randomly between the two memory cards. A refresh operation is usually possible on either cards within a suitable short time interval so that it is seldom necessary to delay a memory access in order to perform a refresh operation. The memory includes a block of addresses that are assigned to a control store and cannot be hashed. The circuit recognizes addresses in this block, and they are not hashed.

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Address Hashing Circuit for Memory with Nonchangeable Address Block

In a system in which a memory has two independently addressable cards and has circuits for simultaneously performing a refresh operation on one card while a normal memory access is made to the other card, a simple address hashing circuit causes memory addresses to occur randomly between the two memory cards. A refresh operation is usually possible on either cards within a suitable short time interval so that it is seldom necessary to delay a memory access in order to perform a refresh operation. The memory includes a block of addresses that are assigned to a control store and cannot be hashed. The circuit recognizes addresses in this block, and they are not hashed. The circuit also recognizes addresses in a mirror section of the memory which would otherwise be swapped with the control store locations by the hashing circuit, and hashing does not occur in this mirror address block.

The drawing shows two memory cards identified as Card 0 and Card 1. Each card has 128K bytes of storage. The two cards are addressed by eighteen address bits 0-17. Low-order bit 17 is used only outside the memory to select one of two bytes in each memory word. Bits 6-16 define addresses within blocks of 4K bytes (on two byte boundaries). Bits 1-5 define 32 blocks on each card, and bit 0 selects one of the two cards. When bit 0 is a binary 0, a memory select signal is generated for card 0 to enable it to respond to address bits 1-16. When address bit 0 is a binary 1, the select signal is generated for card 1.

Unless hashing is inhibited, it is performed by transposing address bits 0 and
16. For example...