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Substrate Voltage Generator with Compensation for Depletion Mode and Enhancement Mode Field Effect Transistors

IP.com Disclosure Number: IPCOM000048220D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Luckett, GC: AUTHOR

Abstract

An enhancement mode voltage detector FET (field effect transistor) has its gate conventionally connected to a reference point to that it conducts in proportion to its substrate voltage, and the voltage at its drain terminal is an error signal for regulating the substrate voltage. To this conventional configuration a depletion mode FET is connected between the positive power supply terminal and the reference voltage point. This FET has its gate connected to its source so that its conduction is a function of its threshold voltage and the substrate voltage. In the conventional detector circuit, the reference voltage is independent of the device characteristics and the substrate voltage. In this circuit, the reference voltage varies with the substrate voltage according to the threshold voltage of the depletion mode FET.

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Substrate Voltage Generator with Compensation for Depletion Mode and Enhancement Mode Field Effect Transistors

An enhancement mode voltage detector FET (field effect transistor) has its gate conventionally connected to a reference point to that it conducts in proportion to its substrate voltage, and the voltage at its drain terminal is an error signal for regulating the substrate voltage. To this conventional configuration a depletion mode FET is connected between the positive power supply terminal and the reference voltage point. This FET has its gate connected to its source so that its conduction is a function of its threshold voltage and the substrate voltage. In the conventional detector circuit, the reference voltage is independent of the device characteristics and the substrate voltage. In this circuit, the reference voltage varies with the substrate voltage according to the threshold voltage of the depletion mode FET. Thus, the error signal from the detector circuit controls the substrate voltage to compensate for manufacturing variations in both the enhancement mode FETs and the depletion mode FETs of the integrated device.

The control voltages that are applied to the gate terminals of the FETs of an integrated circuit device are referenced to a negative voltage that is maintained on the substrate of the device. A substrate voltage generator produces this negative voltage from the positive voltage source that powers the FETs. A capacitor is connected in a bridge switching circuit, and it is switched in one direction to be charged by the positive voltage source and then is switched in the opposite direction to discharge to the substrate in a negative polarity. The switching action occurs, as required, to maintain the desired substrate voltage level. The regulated substrate voltage compensates for variations in FET threshold voltages that occur with variations in the manufacturing process.

FETs 1 through 5 detect the power supply voltage and produce an error signal at a node 7. Enhancement mode FETs 1, 2 and depletion mode FET 5 form a v...