Browse Prior Art Database

Device Controller for Microprocessor Systems

IP.com Disclosure Number: IPCOM000048228D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Compton, JI: AUTHOR [+2]

Abstract

A controller coordinates information transfer between a host device, such as a microprocessor, and a set of controlled devices. The controller establishes a bus for device connection that relies on simple, easy-to-implement protocols.

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Device Controller for Microprocessor Systems

A controller coordinates information transfer between a host device, such as a microprocessor, and a set of controlled devices. The controller establishes a bus for device connection that relies on simple, easy-to-implement protocols.

Referring to Fig. 1, the data bus 10 of the host (not shown) is connected to the normal receiving ports (an 8-bit bus is indicated) of a bidirectional transceiver 12 and a controlled device bus 14 is connected to the transceiver's normal sending ports. Control information is supplied to a decoder 16 by the address bus 18 of the host, and the host "read" and "write" strobe channels (20 and 22, respectively). Based on this control information, the decoder is preferably capable of outputting device command signals for initiating the following types of operation: device address write (AW), data write (DW), data read (DR), status read (SR) and interrupt read (IR).

The particular device commands are communicated to the decoder 16 using memory addresses, and preferably four distinct addresses (denoted MA1-MA4) are used. These memory address signals in conjunction with the read and write strobe signals are identified with corresponding device control signals. The outputs of those device control signals that involve data transfers toward the host (read operations) are combined at an OR gate 20 to produce a signal to control the direction of signal flow through the transceiver 12. Inverters 22 serve to invert the overscore.

Addressing of a particular device is accomplished over the busses 10 and 14, whenever the AW signal is active. Referring to Fig. 2, a device address (e.g., device FE(16) is decoded by a decoder 30 and latches a flip-flop 32, if coincidentally the signal AW is active, to produce the signal...