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Browse Prior Art Database

Data Delay Tolerant F-2F Encoder

IP.com Disclosure Number: IPCOM000048237D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Haas, LC: AUTHOR [+2]

Abstract

This article describes an NRZ to F-2F encoder which is tolerant to delays of nearly 3/4 bit time between data transitions and sampling transitions.

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Data Delay Tolerant F-2F Encoder

This article describes an NRZ to F-2F encoder which is tolerant to delays of nearly 3/4 bit time between data transitions and sampling transitions.

Referring to Fig. 1, data previously loaded into a buffer 10 from a data processing system 12 is normally transferred to an encoder 14 (TX DATA) in response to a TX CLOCK signal from encoder 14. Because buffer 10 and encoder 14 may be remote from one another, there may be a considerable delay or lag between the time a TX CLOCK transition originates within encoder 14 and the time at which the summoned TX DATA actually arrives in encoder 14.

The circuit shown in Fig. 2 can tolerate a delay of nearly 3/4 bit time between the transition in the TX CLOCK signal and the arrival of the TX DATA signal. A TCK signal, which may be symmetrical or asymmetric, is applied both to an inverter 16 and to the trigger input of a device 18, which functions as a divide by two element. Device 18 is shown as a JK flip-flop having both its J and K inputs tied to a source of a logic level 1 voltage. The Q output of such a flip-flop will change states at every other negative-going transition in the TCK signal. The divide function of device 18 could be provided by a transition-sensing binary counter. The output mf device 18 is TX CLOCK, which is transmitted to he buffer 10, shown in Fig. 1, and to one input of a NAND gate 20. The second input to NAND gate 20 is TX DATA, originating within buffer 10. The output of NAND gate 20 is an AK signal which is applied to both the J and...