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Top Isolation Lateral PNP Transistor

IP.com Disclosure Number: IPCOM000048243D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Muggli, RA: AUTHOR

Abstract

This lateral transistor is process-compatible whereby NPN and PNP transistors are readily made with a minimum of fabrication steps. The top isolation diffusion for the two types of transistors is simultaneously carried out for establishing the emitter and collector electrodes for the PNP transistor.

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Top Isolation Lateral PNP Transistor

This lateral transistor is process-compatible whereby NPN and PNP transistors are readily made with a minimum of fabrication steps. The top isolation diffusion for the two types of transistors is simultaneously carried out for establishing the emitter and collector electrodes for the PNP transistor.

A P- substrate 10 has an N+ subcollector 12 deposited therein. About the subcollector is P+ bottom isolation 14 surrounding the subcollector 12. An N epitaxial layer 16 is grown over the previously mentioned parts. P+ top isolation 18 is diffused in the usual manner, but at the same time the same diffusion step establishes the P+ collector 20 and emitter 22, respectively. This N+ diffusion 24 establishes the base electrode.

Fig. 2 is a concentration diagram helpful in an understanding of the process. In this manner the deep diffusion of top isolation material maximizes the lateral emitter area which in turn results in higher Beta and a higher current for high level injection onset. The deeper top isolation diffusion also places the emitter bottom closer to the N+ subcollector 12, which reduces the nonactive emitter downward injection. This also produces a higher retarding E field which reduces recombination in the N+ region.

Fig. 3 shows the compatible NPN lateral transistor. The N+ diffusions are laid down in one fabrication step also. The simplicity in the masking and diffusing steps is readily seen.

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