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Silicon Pin Array Connector for Josephson Package

IP.com Disclosure Number: IPCOM000048259D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Brady, MJ: AUTHOR [+2]

Abstract

Direct electrical interconnections may be made to silicon boards via microminiature alignment and connection pins which are carried within and registered by etched silicon V-grooves.

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Silicon Pin Array Connector for Josephson Package

Direct electrical interconnections may be made to silicon boards via microminiature alignment and connection pins which are carried within and registered by etched silicon V-grooves.

Josephson device packaging requires a new interconnect technology because of its speed and operating environment. In order for this interconnect technology to be manufacturable, it must be simple, reliable, and economical. The present technology, while it is demonstrably functional, is very complex, expensive, and variable in quality.

We describe here a technique which allows these criteria to be met by utilizing etched silicon V-grooves to align microminiature pins. Pins are attached to the silicon by capillary reflow of solder. Drawn wire pins are used to reduce cost, complexity, and contamination problems which characterize the present fabrication processes. The pins are aligned by registration in etched silicon grooves and then rigidly bonded to large cross-sectional area conductors, which can be of dimensions typical of present Josephson conductors.

The current process is shown in Fig. 1. Two right angled silicon boards 10. 12 are bonded together by fillets 14, 16. Socketed pins 18, 20 are inserted into the horizontal board 12. A single silicon board 22 (Fig. 2) could be used instead. Silicon with etched metallized V grooves may be used to register segmented drawn wires with extreme accuracy. These wires 24 may then be bonded in ...