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# Fractional Frequency Division Clock Circuit

IP.com Disclosure Number: IPCOM000048278D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 37K

IBM

## Related People

Miller, EL: AUTHOR [+2]

## Abstract

The present circuit provides clock frequencies which are not exact factors of a master oscillator. This requires division by a fractional number. In order to produce a high accuracy data clock frequency, a mechanism for dividing by a fractional value was developed. Since this is a data clock, minor variations in the instantaneous frequency are tolerable as long as the average frequency is within the specified tolerance. In order to get a long term average frequency with a high accuracy from a master oscillator source, it is necessary to divide a fraction of the form X Y/Z, where X is an integer, Y is the numerator of a fraction, and Z is the denominator.

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Fractional Frequency Division Clock Circuit

The present circuit provides clock frequencies which are not exact factors of a master oscillator. This requires division by a fractional number. In order to produce a high accuracy data clock frequency, a mechanism for dividing by a fractional value was developed. Since this is a data clock, minor variations in the instantaneous frequency are tolerable as long as the average frequency is within the specified tolerance. In order to get a long term average frequency with a high accuracy from a master oscillator source, it is necessary to divide a fraction of the form X Y/Z, where X is an integer, Y is the numerator of a fraction, and Z is the denominator.

In this method of dividing as shown in the figure, two counters are necessary: one to count to X and the other to count to Z. This method works by actually counting to X for Z - Y times and counting to X + 1 for Y times. For every Z cycle of the output, the average is divided by X Y/Z, but for an instantaneous period, the output is either divided by X or X + 1. Counter X is a gated counter clocked from the master source, and counter Z is clocked from counter X. The counters are interconnected, such that for Y decodes of counter Z the input to counter X is disabled for one master clock period.

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