Browse Prior Art Database

Enhanced Programmable Memory Address Registers

IP.com Disclosure Number: IPCOM000048320D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Rehage, TA: AUTHOR [+2]

Abstract

Shown above is an apparatus for loading a fixed offset into the starting address used with memory address registers (MARs). The address is divided into higher-order bits for addressing blocks and lower-order bits for addressing bytes within blocks. At the beginning of each block, the offset address is used to specify the starting point of the bytes within the block. The central processing unit (CPU) only needs to set up the offset value once. Thereafter, at the end of a block and before processing the next block, the initial offset is reloaded into the MARs without interrupting the CPU.

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Enhanced Programmable Memory Address Registers

Shown above is an apparatus for loading a fixed offset into the starting address used with memory address registers (MARs). The address is divided into higher-order bits for addressing blocks and lower-order bits for addressing bytes within blocks. At the beginning of each block, the offset address is used to specify the starting point of the bytes within the block. The central processing unit (CPU) only needs to set up the offset value once. Thereafter, at the end of a block and before processing the next block, the initial offset is reloaded into the MARs without interrupting the CPU.

In operation, MAR1 and MAR2 are the memory address registers which may be selected through multiplexer (MUX) 10 to provide a 13-bit address to access memory. This address is fed back to increment circuit 12 which adds one to the address and passes it to a temporary holding register 14. This incrementation is complete when the register 14 stores the updated address into the previously selected MAR.

The lower-order 8 bits of the address are also passed to compare 16. Compare 16 is looking for the end of block condition. End of block in this memory is defined as a 256-byte boundary. Accordingly, when the lower-order 8 bits indicate that the 256-byte boundary has been reached, an end of block condition is generated by compare 16.

The end of block (EOB) signal is passed to select logic 18 which is used to switch the MUX 20 and MUX 22 in se...