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Minimum Circuit Building Blocks for Parity Circuits

IP.com Disclosure Number: IPCOM000048327D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Frei, AH: AUTHOR [+2]

Abstract

The MOSFET logic circuit provides a basic building block or repeating unit for determining even parity of four or more data bits. The circuit comprises three cross-coupled exclusive-NOR circuits, each one having a separate current limiter as a load device, and an inverter.

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Minimum Circuit Building Blocks for Parity Circuits

The MOSFET logic circuit provides a basic building block or repeating unit for determining even parity of four or more data bits. The circuit comprises three cross-coupled exclusive-NOR circuits, each one having a separate current limiter as a load device, and an inverter.

As shown, the basic four-bit odd parity block consists of three cross-coupled exclusive-NOR circuits, for example, the pair T0 and T1, each one having a separate current-limiting load device, for example, device T4. This three-device circuit has a minimum device count, since there exists no other configuration of elements with fewer devices which can perform the same exclusive-NOR function. At node D, the circuit produces an even parity function of the incoming four-bit word A0-A3. If any one input FET has a sufficiently large voltage drop between its source and gate electrode, current will flow, causing the drain voltage to be low. This results in the exclusive-NOR function for input bits A0 and A1 at node B0 and a corresponding output for bits A2 and A3 at node B1. The resulting signals at nodes B0 and B1 are used as inputs to another exclusive- NOR in the same way.

This circuit handles four bits but may be extended to more than two stages requiring a minimum of log (base 2) N stages, N being the number of input bits.

The use of exclusive-NOR circuits to generate parity is well known.

However, implementation of such minimum device circuits has not been possible for the following reason. If parity is odd, the serially connected devices are conductive and consequently draw current from the current sources. Since the on-resistance of the device is not negligible, each successive stage exhibits a serial voltage drop equal to 1/gm times the number of current sources between the input and the device being considered. The use of multiple stages provides an appreciable voltage drop, degrading the threshold margin of following devices. An additio...