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Insulation Resistance Testing of Printed Circuit Boards

IP.com Disclosure Number: IPCOM000048333D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bozzey, LJ: AUTHOR [+3]

Abstract

Multilayer printed circuit boards containing a high density of printed wire interconnections (nets) can be thoroughly and efficiently tested for insulation resistance (IR) by dividing the printed nets into groups and applying a different voltage to each group.

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Insulation Resistance Testing of Printed Circuit Boards

Multilayer printed circuit boards containing a high density of printed wire interconnections (nets) can be thoroughly and efficiently tested for insulation resistance (IR) by dividing the printed nets into groups and applying a different voltage to each group.

For ease of instrumentation, the cable and card connector sockets serve as the ideal means of grouping and making contact with the board nets. A small quantity of the nets are contacted in each of the sockets using computer assistance which assigns nearly equal quantities of nets per group. It is essential each net be assigned only one bias connection. A different voltage is assigned to each of the voltage planes and each socket group to induce potential faults. The leakage current is monitored between the different voltage bias groups to detect any fault that may develop during environmental conditioning. Boards can be stressed during testing by varying temperature, humidity and voltage.

Failures noted between groups are further isolated as to the individual nets or net and power plane involved by individually scanning the nets within each group.

An arrangement of equipment for testing grouped nets is shown in the figure. A central processor 1 instructs a timing signal generator 2 and a scanner 3 through data coupler 4 in the board test chamber which interconnects the assigned board nets in each socket. The bias voltages are removed, and a test or mea...