Browse Prior Art Database

Attached Processor Directory Assistance

IP.com Disclosure Number: IPCOM000048341D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Drimak, EG: AUTHOR [+4]

Abstract

In an attached processor system that has individual Instruction Processor Units (IPUs) and storage controllers, but has a common main storage, is is necessary of search both directories to determine if either cache contains the requested data. If neither controller has it in its cache, it will be inpaged from main storage. A system of this type is shown schematically in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Attached Processor Directory Assistance

In an attached processor system that has individual

Instruction Processor Units (IPUs) and storage controllers, but has a common main storage, is is necessary of search both directories to determine if either cache contains the requested data. If neither controller has it in its cache, it will be inpaged from main storage.

A system of this type is shown schematically in Fig. 1.

In a storage controller that employs Directory Look-Aside Tables (DLATs), a directory, and a cache, it is necessary to transmit the address of the "missed" data from one subsystem to the other subsystem to determine if that side has the data. An arrangement which provides this function is shown in Fig. 2.

The clocks of the two subsystems may not be in sync due to propagation delays, different clock lengths, etc. Synchronization is achieved in the manner described below. If the data is not present on the other side, no interference is induced es the request is stolen from the opposite side.

In operation, for example, IPU A loads the virtual address and absolute address into the DLAT. IPU A issues a R/W to the storage controller.

The absolute address in the DLAT 3 is compared to the address in the directory 5 and receives a directory miss. This indicates that the requested data is not in cache A. The address and a directory assistance request is transferred to the opposite side via the channels 7. IPU A then enters a Trap Return and will eventually rei...