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Process for Controlling Semiconductor Wafer Warpage

IP.com Disclosure Number: IPCOM000048349D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Schwuttke, GH: AUTHOR [+3]

Abstract

By this process it is possible to obtain convex semiconductor wafer warpage through laser scribing. The process can also be used to compensate convex wafer warpage induced during device fabrication, and thus minimize warpage problems.

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Process for Controlling Semiconductor Wafer Warpage

By this process it is possible to obtain convex semiconductor wafer warpage through laser scribing. The process can also be used to compensate convex wafer warpage induced during device fabrication, and thus minimize warpage problems.

During device fabrication, silicon wafers tend to become warped. Wafer warpage can arise from deposition of surface films, thermal diffusion films, and/or other hot processes. Excessive wafer warpage leads to photolithographic problems and subsequent degradation of device yield. It is therefore important to keep wafer warpage at a minimum.

In this process wafer warpage is minimized by applying stresses to the wafer back side to compensate for the stresses present in the wafer front side. These stresses can be introduced into the back side of the wafer by laser scribing. The degree of convexity can be controlled to a certain extent through laser parameters, such as energy, density and line spacing. The process can be implemented using a Nd-doped YAG laser with a spot size of 115 micrometers with a speed of 25 cm per second, a line spacing of 0.5 mm, a pulse rate of 12 KHz and an energy of 10 joules per sq cm.

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