Browse Prior Art Database

VRC Handling

IP.com Disclosure Number: IPCOM000048356D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+2]

Abstract

This article relates to Vertical Redundancy Code (VRC) generations in transmission and in reception. In the ASCII 7-bit protocol, the characters comprise 7 bits and the eighth bit is always equal to 0. This bit is replaced by an odd parity bit calculated from the 7 bits when the character is sent on the line. This parity bit is checked at the receiving side and reset to 0. This is the Vertical Redundancy Code.

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VRC Handling

This article relates to Vertical Redundancy Code (VRC) generations in transmission and in reception. In the ASCII 7-bit protocol, the characters comprise 7 bits and the eighth bit is always equal to 0. This bit is replaced by an odd parity bit calculated from the 7 bits when the character is sent on the line. This parity bit is checked at the receiving side and reset to 0. This is the Vertical Redundancy Code.

The present proposal is to be used in a communications controller wherein the transfer of data between communication lines and the host central processing unit is controlled by a central control unit through line-scanning devices.

In transmission, the characters to be sent are put in the line-scanning device memory. This memory comprises a ninth odd parity bit calculated from the 8 bits of each character. In the case of ASCII 7-bit characters, the eighth bit being zero, the ninth parity bit is equal to the VRC to be sent. This parity bit is kept during the emission of the character, and it is sent instead of the eighth bit.

When the bits are serialized in order to be sent, the eighth bit transmitted on the line is placed in the first position bit 0.

In reception, the memory parity bit is still used for computing the VRC of the received character. A parity look-ahead circuit computes the memory parity at each received bit. When seven bits have been received, the memory parity is equal to the VRC which is compared to the eighth bit. The receiver...