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Parity Look Ahead in a Shift Register

IP.com Disclosure Number: IPCOM000048357D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+2]

Abstract

In a communication controller wherein the transfer of data between communications lines and host central processing unit is controlled by a central control unit, through line scanning devices, the circuits of these line scanning devices are checked by having an odd parity bit which is added to each byte. This bit is computed through parity look-ahead circuits.

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Parity Look Ahead in a Shift Register

In a communication controller wherein the transfer of data between communications lines and host central processing unit is controlled by a central control unit, through line scanning devices, the circuits of these line scanning devices are checked by having an odd parity bit which is added to each byte. This bit is computed through parity look-ahead circuits.

In scanning devices, a 2-byte shift register is used for deserializing the received bits and recognizing the synchro-pattern, for computing the cyclic redundancy code (CRC) character and for sending the CRC. Three different algorithms are needed for predicting the parity in these three cases.

For the deserialization operation shown in Fig. 1, the received bits are entered in a 16-stage shift register. The parity change algorithm of the first byte is the exclusive OR function of the received bit and bit 7; received bit OR* bit 7. The algorithm for the second byte is the exclusive OR function of bit 7 and bit 15; bit 7 XOR* bit 15.

The CRC is computed according to the scheme of Fig. 2. The same shift register is used and OR exclusive functions are performed between given bits. The parity change algorithm for the first byte is: (received bit (*) bit 15) (*) ((received bit (*) bit 15) (*) bit 4) (*) bit 4 (*) bit 7 which is equal to bit 7.

The parity change algorithm for the second byte is: bit 7 (*) ((received bit (*) bit 15) (*) bit 11) (*) bit 11 (*) bit 15 which is equa...