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Hardware Reduction for Comparing Shift Register and Memory Contents

IP.com Disclosure Number: IPCOM000048360D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+2]

Abstract

This article relates to the reduction of circuits which are required for comparing the contents of a shift register and a memory, specifically in the scanner devices of a communication controller comprising a central control unit controlling the transfer of data between communication lines and a host central processing unit.

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Hardware Reduction for Comparing Shift Register and Memory Contents

This article relates to the reduction of circuits which are required for comparing the contents of a shift register and a memory, specifically in the scanner devices of a communication controller comprising a central control unit controlling the transfer of data between communication lines and a host central processing unit.

In the scanner devices two functions require the comparison of the contents of a shift register and a memory namely, the synchro retrieval function MODE 1 and the CRC (cyclic redundancy code) checking MODE 2. The received bits are deserialized in the shift register and a bit to bit comparison with a pattern stored in the memory is performed in order to recognize the synchro pattern in the binary synchronous control (BSC) protocol. The CRC is computed through a shift register and compared with the CRC computed at the emission side and transmitted on the line. The received CRC is deserialized in the memory and compared with the shift register content to check that the message was transmitted correctly. The memory is read at the beginning of the scanning cycle, and there is rewrite with adequate modification at the end of this cycle. When the last bit of the CRC character is received, the memory only contains the seven first bits. The comparison is done between these seven bits, the received bit (REC. BIT) and the shift register output.

Three switches (SW1, SW2 and SW3) are prov...