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Multi-Emitter Transistor With Schottky Clamp Diode

IP.com Disclosure Number: IPCOM000048369D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Heimeier, H: AUTHOR [+4]

Abstract

Transistor/ transistor logic (TTL) circuits preferably use a multi-emitter input transistor T, according to the equivalent circuit diagram of Fig. 1, with an anti-saturation Schottky clamp diode D between base and collector.

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Multi-Emitter Transistor With Schottky Clamp Diode

Transistor/ transistor logic (TTL) circuits preferably use a multi-emitter input transistor T, according to the equivalent circuit diagram of Fig. 1, with an anti- saturation Schottky clamp diode D between base and collector.

The plan view of Fig. 2A and the sectional view of Fig. 2B show a structural layout of the multi-emitter input transistor with Schottky clamp diode, which has minimum space requirements, maximum symmetry and good tracking characteristics.

An N- epitaxial layer is applied to a P- substrate 1 with N+ subcollector 2. An area of the epitaxial layer, limited by P top isolation 4 and P+ subisolation 5, forms the common N- collector zone 3 of multi-emitter transistor T. Collector zone 3 is connected by a collector contact 6. A common P base zone 7 with finger-shaped extensions 7a is arranged in collector zone 3. Separate N+ emitter zones with emitter contacts 8 are introduced into base zone 7. A continuous contact 9 is arranged transversely to finger-shaped extensions 7a of base zone
7. In the area of each finger-shaped extension 7a, contact 9 forms the ohmic base contact to P base zone 7. In the areas between the finger-shaped extensions, contact 9 forms the anode of Schottky diode D with N- collector zone
3.

In this manner, common contact 9 for the base and the anode can be defined with one mask and be produced with minimum width. The base contact size and the size of the anode of diode D are ind...