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Browse Prior Art Database

Parallel Fail Detect Circuit

IP.com Disclosure Number: IPCOM000048416D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Anolick, ES: AUTHOR [+2]

Abstract

For dielectric studies it is necessary to continuously monitor the samples under test. An incoming voltage spike or an incoming voltage level of either polarity must cause the fail detect circuit to disconnect the device under test and present a signal to a data system.

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Parallel Fail Detect Circuit

For dielectric studies it is necessary to continuously monitor the samples under test. An incoming voltage spike or an incoming voltage level of either polarity must cause the fail detect circuit to disconnect the device under test and present a signal to a data system.

This circuit uses a relay to disconnect the device under test. The coil of the relay is connected to a flip-flop (F/F) on the output side of the fail detect. The input signal is directed to either an inverting circuit IC1 or a non-inverting circuit IC2. The outputs of both ICs are connected to the input of an OR gate IC3. The output of the OR gate is connected to the positive edge-triggered clock line of the F/F. Once a fail signal triggers the F/F, the relay opens, removing the sample from test.

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