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High Order Byte Optimization for Incrementers

IP.com Disclosure Number: IPCOM000048426D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Easter, RJ: AUTHOR

Abstract

Described is a method of reducing the number of circuits and logic levels in the implementation of incremeters used in processor address generation.

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High Order Byte Optimization for Incrementers

Described is a method of reducing the number of circuits and logic levels in the implementation of incremeters used in processor address generation.

In the process of instruction or operand address generation, an incrementer is used to step an address by a specified amount so as to obtain the next double- word or more of information. The step or increment amount can be a positive or negative value, depending on the particular application.

A full 24-bit adder is often used to add or subtract the increment value from an address. However, for addressing purposes, the range of this value is usually from 0 to +255 or from +127 to -127. A single low-order byte can represent these values in twos complement form. Therefore a full adder is not necessary to perform this computation.

The high-order bytes are only a function of the high-order address data, the sign bit of the increment value, and the carry out from the low-order byte add. The implication of this is that the full adder portion of the incremeter need not be larger than the width needed to handle the largest increment value. This greatly simplifies the high-order implementation of the incrementer, as shown in Fig. 1. In addition to simplifying the sum circuits, the parity predict logic is also reduced for the high-order data, as shown in Fig. 2. Further simplification can result by splitting the computation of the high-order data into two parts as shown in Fig. 3.

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