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Asynchronous Multi-Clock Bidirectional Buffer Controller

IP.com Disclosure Number: IPCOM000048430D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Brent, G: AUTHOR [+4]

Abstract

The system indicated in Fig. 1 serves to synchronize transfers bidire-- ctionally between two relatively asynchronous (independently clocked) systems having different width data transfer interfaces.

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Asynchronous Multi-Clock Bidirectional Buffer Controller

The system indicated in Fig. 1 serves to synchronize transfers bidire-- ctionally between two relatively asynchronous (independently clocked) systems having different width data transfer interfaces.

The subject apparatus includes a common buffer controller and buffer memory facility which interface between two separately clocked systems or logical networks C and D. The C and D systems, respectively, supply C and D side clocks to the common apparatus. The C and D systems receive "service request" and "buffer empty" signals from the common apparatus in asynchronous modes. The "buffer empty" signals indicate when the buffers in the common apparatus contain a vacancy. In response to service requests, the C and D systems transfer data and associated "service response" signals.

The handling of the parameters, indicated in Fig. 1, in the common apparatus is indicated below with reference to Figs. 1 and 2.

Set Pointer ("C" Clock): Points to the next buffer available to the "C" side logic. Steps each time a service response from the "C" side is detected.

Reset Pointer ("D" Clock): Points to the next buffer available to the "D" side logic. Steps each time a response is detected from the "D" side.

Data Buffer: Gating to the data bus (C or D side) is controlled by the direction of transfer and the set and reset pointers. Buffer clocking is from the side transferring data to the buffer.

Inbound Transfer: In an inbound ("C" to "D") transfer the set pointer gates the data into the buffer. The data is latched into the buffer when a "C" side response is detected which informs the controller that data is available on the "C" side data bus. If the data path widths on the "C" and "D" sides are equal, a...