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Browse Prior Art Database

Double Channel Wrap

IP.com Disclosure Number: IPCOM000048431D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Brown, PJ: AUTHOR [+3]

Abstract

Connections and circuits described herein permit a central processing system to extensively test the interface signaling effectiveness of associated I/O channels, in a real-time signal-loading environment, on an automated basis and without having to tie up any control units or peripheral devices.

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Double Channel Wrap

Connections and circuits described herein permit a central processing system to extensively test the interface signaling effectiveness of associated I/O channels, in a real-time signal-loading environment, on an automated basis and without having to tie up any control units or peripheral devices.

As shown in the above illustration, a central processing system adaptable for such channel testing operations includes a main store 1, one or more central processing units 2, an input-output processing unit 3, channel interface circuits 4, and channel to control unit interface links 5. Main store 1 is capable of storing programs of instructions for scheduling and initiating input-output operations under control of central processing unit 2, and programs of channel commands for implementing such operations under the direction of processor 3.

Channel circuits 4 are also connected in pairs, via internal "wrap" links 6 and external "wrap links 7, for carrying out the subject testing operations. "Wrap adaptation" circuits 8, which are essentially "additions" to the "normal" complement of interface circuits 4, operate under control of microprograms stored in processor 3 and programs stored in main storage 1 to support the subject testing operations. Circuits 8 are adaptable to operate in four distinct modes; a "normal" mode and three "test" modes "I-III".

In the "normal" mode, a circuit 8 connects associated channel circuits 4 with the associated interface link 5 and processor 3, for conducting "normal" channel communications either with real control units or via external wrap link 7 with circuits 8 in the paired channel unit 4. In test mode I, circuits 8 connect associated channel circuits 4 with internal wrap link 6 and processor 3, for sustaining "normal" channel communications with a paired circuit 8 operating in test mode III. In test modes II and III, circuits 8 are adaptable for emulating the signalling behavior of a broad spectrum of control units and devices, under control of microprograms in processor 3 and programs in main store 1. In test mode II, a circuit 8 connects via the external control unit interface through a manually conne...