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Browse Prior Art Database

Central Processor Stall Alarm

IP.com Disclosure Number: IPCOM000048434D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bullions, RJ: AUTHOR [+3]

Abstract

This is a positive asynchronous test to detect if a Central Processor is stalled or the interface between the Central Processor and a Service Processor (SVP) is broken.

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Central Processor Stall Alarm

This is a positive asynchronous test to detect if a Central Processor is stalled or the interface between the Central Processor and a Service Processor (SVP) is broken.

In a system with an SVP that has a hardware interface to the CP, a polling routine in the SVP will periodically test the hardware interface to the CP. If the CP is not in the Wait or Manual state, a command "Signal If Not Stalled" is issued. This command sets a trigger "Stall Test" in the CP. The CP signals the SVP when it executes its first instruction following the signal. A successful End Op followed by a successful first cycle is considered to be an instruction execution. If the CP does not signal after a predetermined time, then the CP is stalled or the interface is broken.

A CP could be executing an order that exceeds the predetermined time (e.g., interruption loops) or be awaiting an external response. Processor microcode has the capability, when it recognizes such a case, to suppress the detection of stall via use of a special order which causes the stall logic to behave as if an instruction had been executed.

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