Browse Prior Art Database

Dynamic Mapping of Physical and Logical Addresses in Multi-Leaved Storage System

IP.com Disclosure Number: IPCOM000048436D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Sutton, AJ: AUTHOR

Abstract

This article describes: A) The capability to dynamically convert e logical address to a Physical address in an interleaved system, with dynamic addressability. B) The capability to convert physical addresses to logical addresses, as used, for track record purposes, by the Test Block Instruction. Fig. 4 Address bits 7-20 I Form Addr bits 7, 8, 9, 19, 20 I I I Fetch Storage Element Address 000 01 gets Physical UE MAP ID 2nd Entry using BCA Conversion Table (Fig.

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Dynamic Mapping of Physical and Logical Addresses in Multi-Leaved Storage System

This article describes:
A) The capability to dynamically convert e logical address to

a Physical address in an interleaved system, with dynamic

addressability.
B) The capability to convert physical addresses to logical

addresses, as used, for track record purposes, by the Test

Block Instruction.

Fig. 4

Address bits

7-20

I

Form Addr bits

7, 8, 9, 19, 20

I

I

I

Fetch Storage Element Address 000 01 gets

Physical UE MAP ID 2nd Entry

using BCA Conversion

Table (Fig. 3)

I

I

Fetch Respective Using Fig. 3

Physical Map block Example would be

(Fig. 1) 10th entry in Fig. 1

I

I

I

Divide (10-18) by 8

* (gets bit number in block)

I

I

I

Divide by 8

(gets byte & bit in byte)

I

I

I

Set bit entry equals 1

I

I

I

Exit
(*) Bits 19, 20 set to zero since the BCA is set for 4-way

interleaving and each bit represents every other 4th entry.

In a system that has the capability to assign a logical address to variable physical elements, such as described in U.S. Patent 4,280,176, a mechanism is

1

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needed to convert one to the other to maintain a record of data in physical locations in main storage, for example, storage uncorrectable errors (UEs), access power downs, and initial microprogram loads.

Fig. 1 shows the physical storage system which consists of two storage control elements (SE0 and SE1) each having two BSMs (Basic Storage Modules) each. Each BSM is shown with four logical sections, L0-L3, of one megabyte in each section. As described in the referenced patent, a System Controller BSM Configuration Array (BCA) is maintained as a separate table in the System Controller (SC). One image of the BCA is kept in the BCA address conversion table shown in Fig. 3, which has one entry per BCA entry for each one megabyte section in main storage. The contents of the entry contain an SE identifier, a BSM identifier as well as a modifier for levels 0-3 within the BSM.

Fig. 2 shows a physical storage UE map. The UE map uses 1 bit per 2 kilobyte page to indicate which pages have a UE. A 64-byte unit maps the pages in each section. An entry in the conversion table is fetched using requested absolute address bits 7, 8, 9, 19 and 20 which are provided as an input to this mechanism.

A flow diagram of a method to convert a logical address to a physical address is shown in Fig. 4. (see article).

A physi...