Browse Prior Art Database

LSSD Design Multiple Scan Paths

IP.com Disclosure Number: IPCOM000048438D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Siegel, MS: AUTHOR

Abstract

Separate scan paths through the L2 and L3 latches increase circuit use.

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LSSD Design Multiple Scan Paths

Separate scan paths through the L2 and L3 latches increase circuit use.

During normal system time, the L1 system clock is always active. The L1 latch is used as an input to the L2, L3 data input ports. The "data clocks" are gated clocks which steer the data into the desired location. Additional bits of storage can be added to the basic SRL (shift register latch), if desired. However, the reset - 'scan prime clock' will become more complex. In any case, there would be 'N' scan rings, where 'N' is equal to the number of bits associated to one SRL L3(N1) combination.

Thus, in the illustrated embodiment there are two scsn paths, one scan path is through the L1 and L2 latches and the other scan path is through the L1 and L3 latches. Only one path at a time can be scanned.

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