Browse Prior Art Database

Recovery From Errors Due to Slow Array Bits

IP.com Disclosure Number: IPCOM000048439D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Hogan, SG: AUTHOR [+3]

Abstract

In a typical processor, many arrays with compares are used. In most cases the output of the array is compared to known data and a yes/no decision is made. The output is also checked for correct parity. If the array slows down due to a logic failure, an incorrect yes/no decision could be made without an output parity error occurring. This type of failure will result in a non-recoverable program blow-up. A second, delayed comparison for the yes/no decision can solve this problem.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Recovery From Errors Due to Slow Array Bits

In a typical processor, many arrays with compares are used. In most cases the output of the array is compared to known data and a yes/no decision is made. The output is also checked for correct parity. If the array slows down due to a logic failure, an incorrect yes/no decision could be made without an output parity error occurring. This type of failure will result in a non-recoverable program blow-up. A second, delayed comparison for the yes/no decision can solve this problem.

The figure shows a solution to this problem. An additional latch (latch secondary) is added to the logic. It is sampled at a fixed delay after the primary latch. The delay should be about 1/2 to 2 times the array access time. If the primary and secondary latches do not match, an error will be indicated. Therefore, a slow array access would result in a retriable machine check rather than an unrecoverable program failure.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]