Browse Prior Art Database

Edge-Triggered Flip-Flops with Edge-Triggered Clear and Preset

IP.com Disclosure Number: IPCOM000048489D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Hernandez, I: AUTHOR

Abstract

Fig. 1 shows a standard D-type edge-triggered flip-flop with the standard type of preset and clear. The preset and clear inputs are level sensitive. The design shown in Fig. 2 modifies the standard design by adding the circuitry in the dotted squares. This circuitry transforms the level sensitive clear and preset inputs to edge-sensitive inputs. The block diagram of the circuit shown in Fig. 2 is shown in Fig. 3.

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Edge-Triggered Flip-Flops with Edge-Triggered Clear and Preset

Fig. 1 shows a standard D-type edge-triggered flip-flop with the standard type of preset and clear. The preset and clear inputs are level sensitive. The design shown in Fig. 2 modifies the standard design by adding the circuitry in the dotted squares. This circuitry transforms the level sensitive clear and preset inputs to edge-sensitive inputs. The block diagram of the circuit shown in Fig. 2 is shown in Fig. 3.

The new design is useful in generating clocks or enabling signals. As a simple example, assume that there already exist two or more enabling signals A and B, as shown in Fig. 4. However, another enabling signal is required whose activity state corresponds to the leading (or trailing) edge of the two already existing signals A and B. In particular, assume that an enabling input signal C is required whose active state corresponds to the leading edge of signal A and to the trailing edge of signal B. As shown in Fig. 3, signal A is applied to the clock (CLK) input, and signal B is applied to the preset input. When signal A goes from a 0 to a 1, it clocks in the 0 at the D input, thereby enabling input signal C to become active, in this case a 0. To terminate output signal C, the trailing edge of signal B is used to preset output signal C back to its inactive state.

The new design allows either the preset or the clear inputs of a flip-flop to precisely determine the point at which a generated cloc...