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Interface Definition For Direct Memory Access Support

IP.com Disclosure Number: IPCOM000048518D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Magrisso, IB: AUTHOR

Abstract

The interface control sequences required by a Direct Memory Access (DMA Controller and associated input/output (I/O) devices and storage are described. This interface minimizes the number of steps in the data transfer sequence and the pins required by the DMA Controller. the Controller is the master during the data transfer operation. This approach requires that the DMA Controller act as an intermediary, and therefore adds a performance burden as well as I/O pins to the DMA Controller. On a Storage Read operation, the Controller must do a Read operation to Storage and a Write operation to a Device. On a Storage Write operation, the Controller first does a Read from the Device and then a Write to Storage. The amount of performance penalty depends on how well synchronized all the components are.

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Interface Definition For Direct Memory Access Support

The interface control sequences required by a Direct Memory Access (DMA Controller and associated input/output (I/O) devices and storage are described. This interface minimizes the number of steps in the data transfer sequence and the pins required by the DMA Controller. the Controller is the master during the data transfer operation. This approach requires that the DMA Controller act as an intermediary, and therefore adds a performance burden as well as I/O pins to the DMA Controller. On a Storage Read operation, the Controller must do a Read operation to Storage and a Write operation to a Device. On a Storage Write operation, the Controller first does a Read from the Device and then a Write to Storage. The amount of performance penalty depends on how well synchronized all the components are. In the present scheme, the above- mentioned penalty is eliminated by designating the Controller as the master of any operation being performed.

A representative system is shown in Fig. 1. It includes DMA Controller 1, Storage 2, a separate Microprocessor/Arbiter 3 and I/O Devices 4 and 5. The I/O Devices require support for Direct Memory transfers. The DMA Controller 1 supports this function by providing the address registers for transfers to and from Storage 2. Communications that are required between the components during a memory transfer are described here. A more detailed representation of the signals needed between Controller 1, Microprocessor/Arbiter 3, and I/O Device 4 is shown in Fig. 2. Signal sequences are shown in Fig. 3.

The function of DMA Controller 1 is to provide the addressing pins and logic as well as counters and registers required in this operatio...