Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Parallel Interface To Scanned Keyboard

IP.com Disclosure Number: IPCOM000048561D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bealle, F: AUTHOR

Abstract

Portable battery powered keyboard input computing devices, such as programmable calculators and microcomputers, typically use volatile memories store input data and program steps. Shutting off the device to conserve battery life loses all input data and programming so that reentry is required on subsequent start-up. The parallel to serial interface proposed herein allows convenient data entry and reentry without using the device's keyboard directly.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Parallel Interface To Scanned Keyboard

Portable battery powered keyboard input computing devices, such as programmable calculators and microcomputers, typically use volatile memories store input data and program steps. Shutting off the device to conserve battery life loses all input data and programming so that reentry is required on subsequent start-up. The parallel to serial interface proposed herein allows convenient data entry and reentry without using the device's keyboard directly.

Fig. 1 illustrates a simple schematic of a typical computing device using scanning techniques to derive information from keyboard 1 composed of an n times m matrix of switches. Scanning permits all n times m switches to be input to the calculator chip 2 of the computing device with only m CPU chip input terminals using n sequential scans. The novel parallel interface disclosed herein replaces a serial (one key stroke per scan cycle) structure by a parallel interface structure which allows up to n+m inputs per scan cycle.

Referring to Fig. 2, the parallel interface shown is connectable to the n scan lines and m CPU input lines of a computing device. The n plus m signal leads conveying signals t(1) to t(8) and t(n). Lambda(n) are used to "gate" or control analog switches S(1) to S(13) which permit n+m external Lambda(1) to Lambda(8), Lambda(A) to Lambda(E) signals to be input to the CPU chip. For successful operation of the parallel interface, the external signals presented may be...