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Print Hammer Error Checking

IP.com Disclosure Number: IPCOM000048567D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Carrington, JE: AUTHOR [+2]

Abstract

Print hammer driver circuits are checked for error where the turn-on and turn-off times are delayed and operate asyncronously from the print control unit timings.

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Print Hammer Error Checking

Print hammer driver circuits are checked for error where the turn-on and turn-off times are delayed and operate asyncronously from the print control unit timings.

The sequence of events for checking hammer driver circuits which have variable hammer driver turn-on and turn-off times is as follows:
1. Prior to a print and belt data comparison, and during the time

that each print position is addressed or optioned, the on/off

status of the hammer driver is checked for an off condition by

gating a hammer echo (HMR ECHO) signal through AND gate 10,

under control of an ENABLE bit, to hammer misfire latch 11.

The ENABLE bit is generated from check buffer 12 for the

specific print position addressed. If the HMR ECHO signal

indicated that the hammer driver was on, then a hammer misfire

error is generated by latch 11. If a HMR ECHO signal did not

indicate the hammer driver was on, then latch 11 remains in

the reset state and no hammer misfire signal is generated.

This process is repeated each scan time that the print position

is addressed until such time as a comparison of the print and

belt data occurs.
2. When the print and belt data comparison matches, a compare

signal 13 (Fig. 2) is generated. This signal turns off the

check window line and turns on the FIRED bit in check buffer

12. For each subsequent addressing of that hammer position, a

check window count contained in buffer 12 is incremented.

This continues until a hammer check count is reached, whereupon

comparator 14, responsive to a stored check count in register

15, generates an EQUAL pulse gating FIRED bit from check

buffer 12 through AND gate 16 to AND gate 17. T...