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Variable Control of Print Hammer On-Time

IP.com Disclosure Number: IPCOM000048568D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gibb, RE: AUTHOR [+2]

Abstract

Line printers fire a hammer or a group of hammers at different time intervals within a single print line. Fire point is determined according ing to when selected characters align with proper hammers for the positions to be printed. With the fire point fixed because of character alignment, turnoff point in time can be made variable for density control. For a fixed hammer ON duration, this is achieved by storing the hammer address number in a programmable shift register or FIFO (first-in, first-out) memory. The control then clocks through all the shift register positions until the hammer number later appears at the output in clock cycles for hammer resetting. The ON-time is thereby determined by the shift register length times the period of the shift register clock.

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Variable Control of Print Hammer On-Time

Line printers fire a hammer or a group of hammers at different time intervals within a single print line. Fire point is determined according ing to when selected characters align with proper hammers for the positions to be printed. With the fire point fixed because of character alignment, turnoff point in time can be made variable for density control. For a fixed hammer ON duration, this is achieved by storing the hammer address number in a programmable shift register or FIFO (first-in, first-out) memory. The control then clocks through all the shift register positions until the hammer number later appears at the output in clock cycles for hammer resetting. The ON-time is thereby determined by the shift register length times the period of the shift register clock.

Random-access memory (RAM) 10 used as a shift register or FIFO storage means must always do a read and then write for each clocking cycle of counter 11, as shown in Fig. 2. which addresses the RAM. The range over which counter 11 runs is determined by the value programmed into RAM 10 on Data In bus 12. RAM 10 contains the programmed value of the delay. This would be defined by the expression Delay Value /Clock Rate equals Delay Count. Delay Count is established by register 14 and a compare circuit 15 connected to counter 11. When the delay count in register 15 equals the count in counter 11, compare circuit 16 generates a reset to counter 11. Counter 11, driven b...