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Up/ Down Ripple Counter

IP.com Disclosure Number: IPCOM000048571D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 81K

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Cheng, PH: AUTHOR [+2]


An N-bit up/down ripple counter is implemented with cascode current switch latches in a master-slave arrangement.

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Up/ Down Ripple Counter

An N-bit up/down ripple counter is implemented with cascode current switch latches in a master-slave arrangement.

Fig. 1 is a functional block diagram of such a counter 10, where N equals 4, for example. The circuit schematic for the first stage 11, i.e., the least significant bit (LSB) stage, is shown in Fig. 2. Except for stage 11, each of the successive higher-order bit stages 12-14 are identically configured with the circuit schematic of Fig. 3.

With the switches S1-54 (Fig. 2) of stage 11 and S5-S10 (Fig. 3) of stages 12-14 in the illustrated positions, the respective outputs Aout, Bout, Cout and Dout (Fig. 1) of counter 10 are directly presettable to their logical 1 states. Alternatively, in the alternate positions of switches S1-S10, which are shown merely for purposes of explanation, the outputs Aout-Dout are selectively presettable to some desired count by the preset circuits 15 and 16 of Figs. 2 and 3, respectively, in response to the respective binary input signals INPUT A- INPUT D (Fig. 1) applied to the respective inputs IN of stages 11-14. In either case, when the counter 10 is being preloaded, i.e., preset, enable signal ENABLE, which is commonly applied to the inputs E of stages 11-14, is at its logical 0 level.

As shown in Fig. 2, stage 11 has a count down (D) portion 11D and a count up (U) portion 11U, each of which in turn has a pair of master (M) and slave (S) cross-coupled latches ADM/ADS and AUM/AUS, respectively. Each of the stages 12-14, likewise, have count down (D) and count up (U) portions designated generally in Fig. 3 as nD/nU, and the master (M) and slave (S) latches being designated generally therein as nDM/nDS and nUM...