Browse Prior Art Database

Reduction of Overlap Capacitance and Delta L

IP.com Disclosure Number: IPCOM000048581D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

The source-drain implant in the standard double polysilicon process is done after screen silicon dioxide layer 10 is grown. The screen silicon dioxide is typically grown in oxygen and HCl at 925 degrees C. The screen silicon dioxide and second layer of polysilicon sidewall silicon dioxide layer 11 are both about 250 A thick.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Reduction of Overlap Capacitance and Delta L

The source-drain implant in the standard double polysilicon process is done after screen silicon dioxide layer 10 is grown. The screen silicon dioxide is typically grown in oxygen and HCl at 925 degrees C. The screen silicon dioxide and second layer of polysilicon sidewall silicon dioxide layer 11 are both about 250 A thick.

To reduce overlap capacitance in the polysilicon gated device, the screen silicon dioxide layer is grown at 800 degrees C in O(2), H(2)O and HCl. This increases the sidewall silicon dioxide thickness from about 250 A to about 750 A. Since the sidewall silicon dioxide masks the source-drain implant, the gate electode 13 to diffusion overlap capacitance will be reduced. In addition, Delta L (L mask to L wafer) will also be reduced. Further reduction in overlap capacitance and Delta L can be achieved by increasing the screen silicon dioxide thickness to, for example, 450 angstroms.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]