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High Breakdown Voltage Junction For Protective Device in Polysilicon Recessed Oxide Technology

IP.com Disclosure Number: IPCOM000048606D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR [+3]

Abstract

Specifications on the turn-on or breakdown voltage of the input junction of protective devices (PDs), used to shunt electrostatic voltage (ESV) away from thin silicon dioxide regions, must lie within a range whose lower and upper bounds are generally determined by the following factors: the lower bound must be larger than the maximum signal voltage to be received by the thin oxide, and the upper bound must be below the minimum thin oxide breakdown voltage minus an allowance for IR drop in the PD.

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High Breakdown Voltage Junction For Protective Device in Polysilicon Recessed Oxide Technology

Specifications on the turn-on or breakdown voltage of the input junction of protective devices (PDs), used to shunt electrostatic voltage (ESV) away from thin silicon dioxide regions, must lie within a range whose lower and upper bounds are generally determined by the following factors: the lower bound must be larger than the maximum signal voltage to be received by the thin oxide, and the upper bound must be below the minimum thin oxide breakdown voltage minus an allowance for IR drop in the PD.

In practice, logic and memory circuits generate compatible bounds so that a single PD structure is sufficient. Special circuits, however, may require bounds incompatible with those of logic and memory and two types of PDs with different turn-on voltage will be needed for a given technology. The turn-on voltage of most PD structures is strongly determined by the avalanche breakdown voltage of its input junction (BVJ). The present description shows two types of p/n junction structures having the high BVJ needed to protect EPROM (Eraseable Programmable Read-Only Memory) cells. EPROM cells require lower and upper bounds determined by the following considerations:
Lower bound: Since the voltage signal to charge an EPROM floating gate is about 25 V, the PD input junction

must have a BVJ higher than needed for logic or

memory.

Upper bound: Fig. 1 shows the connection of a PD to an EPROM cell. ESV appears across the series combination of

1200 (Angstrom) and 450 (Angstrom) oxides. To

protect this combination, the PD input

junction must break down below 75 V.

Fig. 2 compares PD turn-on voltage ranges required by logic, memory and EPROM fabricated using state of the art, polysilicon, recessed oxide technology. It is clear that PD structures of low and high turn-on voltage are needed to satisfy these requirements.

The key steps in fabricating one type of high BVJ structure are shown in Figs 3, 4 and 5. Fig. 3 shows a recessed oxide isolation 12 surrounding a monocrystalline silicon region 14 having a thin silicon dioxide layer 16 thereover. A boron (B) ion implantation is shown for the usual threshold adjustment. Fig. 4 shows the ion implantation of arsenic (As) to compensate the boron and form an n layer 18. The purpose of this n layer will be explained below. An opening is made in the layer 16 where the n+ region of high BVJ is desired. The structure uses a phosphorous-doped n+ polysilicon layer 20 to form the n+ region 22 by outdiffusion, as shown in Fig. 5, and also to provide a buried contact thereto.

The structure of Fig. 5 is completed by covering it with a glass layer, opening contact holes, and forming metal interconnections from pads to the buried polysilicon contact and to the gates to be protected.

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