Browse Prior Art Database

Memory Data Steering Using On-Chip Switching Network And Off-Chip Control Network

IP.com Disclosure Number: IPCOM000048610D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Cavaliere, JR: AUTHOR [+5]

Abstract

A method of switching in redundant memory bit positions in substitution for known defective bit positions is described. The method utilizes off-chip programmable wiring to provide static signal inputs to the chip. These inputs activate and control circuits on the chip to effect the bypassing of defective bit positions and their replacement with substitute bit positions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Memory Data Steering Using On-Chip Switching Network And Off-Chip Control Network

A method of switching in redundant memory bit positions in substitution for known defective bit positions is described. The method utilizes off-chip programmable wiring to provide static signal inputs to the chip. These inputs activate and control circuits on the chip to effect the bypassing of defective bit positions and their replacement with substitute bit positions.

Programmable signal inputs to the chip are provided by using the laser delete link facility on the module. The module facility shown in Fig. 1 may be used to program a chip input to either -0.6 V (down level) or plus 0.3 V (up level).

Assume, for example, that 16384 bits of storage per chip are required. Assume also that four chip data imput lines 1 are multiplexed by a one out of 4096 select circuit 2 and that two-chip data output lines 3 are multiplexed by a one out of 8192 select circuit 4, as shown in Fig. 2. Redundancy is achieved by the addition of 2048 extra bits 5 and control gates 6 and 7. In Fig. 2, the 4 data input lines 1 are first multiplexed into 8 lines. These 8 lines are connected to 9 lines through switching network 6 comprising 16 gates. Each of the 9 lines is multiplexed into a respective memory section comprising 2048 bits of storage. Similar gates are inserted between storage and the chip data output terminals 3.

By control of the gates 6 and 7, any 8 of the 9 blocks of storage may be selected fo...