Browse Prior Art Database

Folded Bit Line Connection To Sense Latch

IP.com Disclosure Number: IPCOM000048622D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Arzubi, L: AUTHOR

Abstract

The prior-art circuit in Fig. 1 consists of a monolithic integrated circuit with a semiconductor substrate. Bit lines 1 and 2, connected to sense latch 3 and simultaneously acting as source zones for FETs (field effect transistors) 4, are made up of elongated diffusion zones in the semiconductor substrate. FETs 4 include part of the single diffusion zones in the semiconductor substrate between bit lines 1 and 2 and the gate electrodes made up of word lines 6 crossing bit lines 1 and 2 from which they are insulated. The single diffusion zones also act as capacitors 5 between the drains of FETs 4 and the semiconductor substrate covered by a thin oxide layer which additionally serves as a gate oxide in the appropriate places.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 74% of the total text.

Page 1 of 2

Folded Bit Line Connection To Sense Latch

The prior-art circuit in Fig. 1 consists of a monolithic integrated circuit with a semiconductor substrate. Bit lines 1 and 2, connected to sense latch 3 and simultaneously acting as source zones for FETs (field effect transistors) 4, are made up of elongated diffusion zones in the semiconductor substrate. FETs 4 include part of the single diffusion zones in the semiconductor substrate between bit lines 1 and 2 and the gate electrodes made up of word lines 6 crossing bit lines 1 and 2 from which they are insulated. The single diffusion zones also act as capacitors 5 between the drains of FETs 4 and the semiconductor substrate covered by a thin oxide layer which additionally serves as a gate oxide in the appropriate places.

However, this approach requires interleaved word line wiring and thus additional bit line capacitance. As shown in Fig. 1, bit lines 1 and 2 are extended, so that the word line sections not used for gate connections are crossed at sites 7. This leads to larger storage nodes for maintaining the transfer ratio and thus to a loss in real estate, caused by the increase in inactive semiconductor areas, and to a correspondingly reduced chip density.

These problems are eliminated by an additional wiring level. In Fig. 2, bit lines 1' and 2' are also elongated diffusion zones in a semiconductor substrate. These lines are positioned rectilinearly rather than parallel to each other, leaving a suitable gap between...