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Browse Prior Art Database

Metal Lift Off Process With A Self Aligned Insulation Planarization

IP.com Disclosure Number: IPCOM000048640D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Hoeg, AJ: AUTHOR [+3]

Abstract

This article describes a metal lift-off process employing silicon nitride layers and a reactive ion etching process to provide a planar layer of insulation to support a second level of metal.

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Metal Lift Off Process With A Self Aligned Insulation Planarization

This article describes a metal lift-off process employing silicon nitride layers and a reactive ion etching process to provide a planar layer of insulation to support a second level of metal.

Referring to Fig. 1, a semiconductor substrate 10 is shown.

The substrate 10 may have exposed gate oxide regions or other suitable diffusions. A layer 12 of silicon nitride is formed on the substrate 10 using plasma-enhanced chemical vapor deposition (PECVD). The thickness of layer 12 is approximately equal to the desired thickness of a metal layer to be formed. A photoresist 14 is formed over the plasma nitride layer 12, and patterns are defined in the resist where metal lines are to be formed on the substrate 10. A dry etching technique (preferably reactive ion etching followed by plasma etching) using DE 100 gas is used to remove the plasma nitride in the vicinity of the exposed windows in the photoresist 14. A controlled amount of overetch is used in the nondirectional etch conditions to provide an overhanging photoresist pattern at the edges of the window.

Referring to Fig. 2, a layer 16 of metal is evaporated onto the structure. A metal pattern 18 is deposited directly on the substrate 10 in the window, leaving gaps 20 on either side of the metal 18.

Referring to Fig. 3, the photoresist layer 14 is stripped, carrying away the excess metal 16, leaving only metal 18 in close proximity to the surrounding areas of the plasma nitride layer 12.

Referring to Fig. 4, the planarization process is begun by depositing a second layer 22 of silicon nitride using the same PECVD conditions as existed in depositing the first layer. The second layer, whose thickness is preferably one- half the width of the gap to be filled, conforms to the topography of the previously-formed structure.

Referring to Fig. 5, a reactive ion etching (RIE) process is used...