Browse Prior Art Database

Interrupt Generator Device

IP.com Disclosure Number: IPCOM000048681D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Glembocki, J: AUTHOR

Abstract

This system is capable of expanding the interrupt handling capacity of a distributed interface system and eliminates the extensive amount of polling by the CPU required to identify interrupts. In addition, it eliminates the need for the CPU to identify a pending interrupt since an encoded interrupt is presented to the CPU. This system also makes use of bidirectional interrupts, which can be a more efficient way of posting events to the CPU.

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Interrupt Generator Device

This system is capable of expanding the interrupt handling capacity of a distributed interface system and eliminates the extensive amount of polling by the CPU required to identify interrupts. In addition, it eliminates the need for the CPU to identify a pending interrupt since an encoded interrupt is presented to the CPU. This system also makes use of bidirectional interrupts, which can be a more efficient way of posting events to the CPU.

Elements of the system, as shown in the drawing, include:
1. A 16-bit parallel in, parallel out, serial in clocked

shift register 11.
2. A 16-bit parallel in, serial out clocked shift register 12.
3. A clock oscillator 13 and a five-bit counter 14.
4. Digital logic gates and dip switches.
5. A stack memory 16 with tristate output which will sample the

bus to check if busy before outputting data. Output may also

be initiated through an additional request line, thus

eliminating the bus busy check. Stacking can be

first in, first out, or last in, first out, depending

on the application.

The memory stack can be either hardware or a microcomputer.

Clock pulses of 50 percent duty cycle are generated and counted by fivebit counter 14. Counts are updated on the (+) transition of the clock CL. Counter bit C0 is the most significant. On every (+) transition of CO, new data is clocked into the first shift register 11 while the previous data A0-A15 is passed through to the second register 12. The contents of these two registers now represent two "snapshots" of the inputs at two different times.

While C0 is still high, C1 is used to shift down both registers. The A0 and B0 bits are compared. Bits C1 through C4 contain the count of the bit in the A0B0 positions. The exclusive 0R gate 17 compares A0 and B0 to detect changes. If a change is present and the proper (+) or (-) detect switch is active (on), then a load into stack memory is enabled and occurs at the (-) transition of C1.

Memory 16 is loaded with the address of the bit that changed, into the lowest- order four bits of the word (this is the counter output bits C1 through C4). The next three bits of memory are load...