Browse Prior Art Database

Software/ Hardware Approach To Dynamic Memory Refresh

IP.com Disclosure Number: IPCOM000048706D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Boyd, CE: AUTHOR [+4]

Abstract

Dynamic memory chips require a periodic read of each column or row to assure data integrity. Most solutions to this problem use a strictly hardware approach. A timer usually signals a refresh request. When the refresh cycle is granted, the current refresh address is gated onto the address bus and a refresh cycle is performed by the timing and control logic. The refresh counter, multiplexer, timing and control logic are commercially available on a single MSI (medium scale integration) logic module.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 2

Software/ Hardware Approach To Dynamic Memory Refresh

Dynamic memory chips require a periodic read of each column or row to assure data integrity. Most solutions to this problem use a strictly hardware approach. A timer usually signals a refresh request. When the refresh cycle is granted, the current refresh address is gated onto the address bus and a refresh cycle is performed by the timing and control logic. The refresh counter, multiplexer, timing and control logic are commercially available on a single MSI (medium scale integration) logic module.

The disclosed approach is a radical departure from the above classical approach. The processor address lines are used as the address generator so that no multiplexer or refresh counter is required. The basic concept in this approach is to simultaneously perform a refresh operation on the RAM (random- access memory) when a read operation is performed on the ROS (read-only storage), using the same address.

Referring to the figure, the interval of the timer 1 is set to the RAM refresh period. The timer interrupts the processor 2, which executes a program in ROS 4 through decode 3. The decode 3 includes address decode and control logic for providing the necessary control signals to the ROS 4 and RAM 5. During each ROS access, the data bus is isolated from the RAM 5 via its data buffer 6 and a read or refresh program is performed on the RAM 5. The refresh program is a simple program which merely reads the required number...