Browse Prior Art Database

Synchronous LSSD Packet Switching Memory And I/O Channel

IP.com Disclosure Number: IPCOM000048708D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Jeremiah, TL: AUTHOR [+4]

Abstract

With increasingly complex systems, automatic test pattern generation with good testability is required for manufacturing as well as minimizes development schedule risks. A synchronous memory and I/O channel that conforms to LSSD (Level Sensitive Scan Design) methodology satisfies this criterion. However, in many cases this methodology burdens the system to the point that performance is significantly impaired. Often this turns out as a trade-off between performance and testability. The approach described here is compatible with LSSD and achieves an extremely high performance of 20 mbytes interconnecting FET devices.

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Synchronous LSSD Packet Switching Memory And I/O Channel

With increasingly complex systems, automatic test pattern generation with good testability is required for manufacturing as well as minimizes development schedule risks. A synchronous memory and I/O channel that conforms to LSSD (Level Sensitive Scan Design) methodology satisfies this criterion. However, in many cases this methodology burdens the system to the point that performance is significantly impaired. Often this turns out as a trade-off between performance and testability. The approach described here is compatible with LSSD and achieves an extremely high performance of 20 mbytes interconnecting FET devices.

The figure shows a simplified timing diagram for channel operation. The channel is synchronous with two transfers possible each processor cycle. However, any given logic device performs only one function each cycle. Only the channel is multiplexed. The first half of each cycle is dedicated to address requests, and the second half is shared between data replies and data to be written. Each operation uses one of the two cycle halves, for example, a read request and reply of data or a write request with the data to be written.

A tag field is sent with each read request so the requester is identified. The same tag is sent back with the requested data during a reply to identify it. In this way several requests can be outstanding at any one time either from several requesters or a single requester. Thi...