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Minimum And Maximum Detector

IP.com Disclosure Number: IPCOM000048733D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Yosim, PS: AUTHOR

Abstract

Switches are employed to utilize the same circuitry for detecting both the minimum and maximum signal levels of a varying wave.

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Minimum And Maximum Detector

Switches are employed to utilize the same circuitry for detecting both the minimum and maximum signal levels of a varying wave.

The circuit differs from a standard minimum or maximum detector in that it uses the same amplifiers, resistors, and capacitors for measuring ing both the minimum and the maximum, thus improving immunity to effects of circuit irregularities, and the holding capacitor is automatically set to a proper initial condition. The essence of the circuit is a standard peak detector 10 with the difference being that two diodes D1 and D2 are used to control charging of the holding capacitor where each is switched in or out at the proper time to configure the circuit either as a peak or valley detector.

A sine-wave voltage to be detected is supplied from detector and amplifier A1 at A. A low-pass filter R5, C2 extracts the average DC level of the signal B. This is compared with the raw signal by C2 to generate a digital signal C that is high when peaks should be looked for and low when valleys should be sought out.

Comparator C3 and associated components form a high frequency clock which clocks shift register Ll via signal D. The peak/through control signal C is clocked through the shift register. Exclusive OR gate L2 in conjunction with L1 create pulses out of all edges of signal C. These pulses E are inverted by L4 and made compatible to a particular logic family by T1 before driving the start convert line of an A/D (ana...