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Delay Line Controlled Channel To Channel Data Transfer Mechanism

IP.com Disclosure Number: IPCOM000048757D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Firth, SR: AUTHOR [+2]

Abstract

I/O device or channel design for certain data processing systems must contend with the problem of synchronizing data tags with their internal clocking mechanism. In the case of a channel, the data tags must eventually be synchronized with storage clocking. In the case of I/O devices, the data tags must be synchronized with the clocking of the storage media (tape, disks, etc.). This is particularly troublesome because metastability must be taken into account anytime that an asynchronous tag has to be synchronized with a clock timing pulse during the possible period of instability following the sampling. The usual solution is to wait over this metastable duration before actually using the asynchronous data.

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Delay Line Controlled Channel To Channel Data Transfer Mechanism

I/O device or channel design for certain data processing systems must contend with the problem of synchronizing data tags with their internal clocking mechanism. In the case of a channel, the data tags must eventually be synchronized with storage clocking. In the case of I/O devices, the data tags must be synchronized with the clocking of the storage media (tape, disks, etc.). This is particularly troublesome because metastability must be taken into account anytime that an asynchronous tag has to be synchronized with a clock timing pulse during the possible period of instability following the sampling. The usual solution is to wait over this metastable duration before actually using the asynchronous data. At a high sample rate, the metastable period becomes comparable to the data transfer period, thus requiring complex buffering and controls. In particular, with a channel-to-channel adapter, the cost and complexity of a high speed design becomes formidable. problem in a simple, economical way. Unlike known I/O control units or channel designs, a channel-to-channel adapter has no need to synchronize the data with its internal clocking. However, clocking is required to move the data through the channel-to-channel adapter hardware. This arrangement provides complete clocking from the asynchronous tags themselves, thereby eliminating the metastability problem. Buffering and associated controls are not required, and the same mechanism will handle either DC interlocked or data streaming protocols.

A design that is used in the synchronizing channel-to-channel adapter utilizes electromagnetic delay lines to control the data handling. Data tags from the channel are passed through delay lines and control pulses are logically created, as shown in Fig. 1. Similarly, the interface between the two channels uses delay lines to synchronize the data transfer. A brief functional description follows.

The adapter (SCCA (Synchronizing Channel-to-Channel Adapter)) requires that one channel write data to the control unit and that the second channel read data. Each channel connects to the adapter using a conventional selection sequence. The adapter port (side) receiving the data is designated as the "write" port. The complementing port sending the data is declared the "read" port. The designations read port and write port are always in reference to the attached channel, as indicated in Fig. 2.

Fig. 3 is a timing diagram for the arrangement. The data transfer always begins with the write port. It signals the channel...