Browse Prior Art Database

Interlevel Chip Metallization

IP.com Disclosure Number: IPCOM000048762D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Dalal, HM: AUTHOR [+3]

Abstract

Silicon wafers which have completed hot processing are next subject to personalization to interconnect the various devices into circuits on the chip. Due to high device density on the chip, multilevel metal layers interconnected through vias in the intervening passivation layers are used. Considerable thinning of the Al-4 percent Cu interconnecting metallurgy has been observed to occur on via sidewalls. This is especially so in reactively ion etched vias, as in such vias the sidewalls are especially steep. The thinned sidewalls have been determined to be prone to failure due to electromigration.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Interlevel Chip Metallization

Silicon wafers which have completed hot processing are next subject to personalization to interconnect the various devices into circuits on the chip. Due to high device density on the chip, multilevel metal layers interconnected through vias in the intervening passivation layers are used. Considerable thinning of the Al-4 percent Cu interconnecting metallurgy has been observed to occur on via sidewalls. This is especially so in reactively ion etched vias, as in such vias the sidewalls are especially steep. The thinned sidewalls have been determined to be prone to failure due to electromigration.

A layer of water bled Cr, preferably 100-200 nm thick, deposited as an underlay to the standard Al-4 percent Cu metallization, has been evaluated and is illustrated in the figure.

Such a metallization system is demonstrated to improve the electromigration resistance at the interlevel vias considerably, possibly by the "laminate" structure effect: the underlying highly electromigration resistant water bled Cr shares an increasingly larger share of the via current as A1-4 percent Cu metallurgy depletion occurs in the via. For similar reasons, the water bled Cr/Al-4 percent chip metallurgy is also determined to improve chip reliability as such a metallization system is demonstrated to be more tolerant of metallization defects.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]